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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 mos integrated circuit m m m m pd441000l-x 1m-bit cmos static ram 128k-word by 8-bit extended temperature operation data sheet document no. m13714ej4v0ds00 (4th edition) date published march 1999 ns cp (k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd441000l-x is a high speed, low power, 1,048,576 bits (131,072 words by 8 bits) cmos static ram. the m pd441000l-x has two chip enable pins (/ce1, ce2) to extend the capacity. the m pd441000l-x is packed in 32-pin plastic sop, 32-pin plastic tsop (i) and 36-pin plastic fpbga. features 131,072 words by 8 bits organization fast access time: 70, 85, 100, 120, 150 ns (max.) low voltage operation (b version: v cc = 2.7 to 3.6 v, c version: v cc = 2.2 to 3.6 v, d version: v cc = 1.8 to 3.6 v) operating ambient temperature: t a = C25 to +85 c output enable input for easy application two chip enable inputs: /ce1, ce2 supply current part number access time ns (max.) operating supply voltage v operating ambient temperature c at operating ma (max.) at standby m a (max.) at data retention m a (max.) m pd441000l-bxxx 70, 85, 100 2.7 to 3.6 - 25 to +85 25 2 2 m pd441000l-cxxx 100, 120 2.2 to 3.6 m pd441000l-dxxx 120, 150 1.8 to 3.6 ? ? ? ?
data sheet m13714ej4v0ds00 2 m m m m pd441000l-x ordering information part number package access time ns (max.) operating supply voltage v operating temperature c remark m pd441000lgw-b70x 32-pin plastic sop (525 mil) 70 2.7 to 3.6 - 25 to +85 b version m pd441000lgw-b85x 85 m pd441000lgw-b10x 100 m pd441000lgw-c10x 100 2.2 to 3.6 c version m pd441000lgw-c12x 120 m pd441000lgw-d12x 120 1.8 to 3.6 d version m pd441000lgw-d15x 150 m pd441000lgu-b70x-9jh 32-pin plastic tsop (i) 70 2.7 to 3.6 b version m pd441000lgu-b85x-9jh (8 x 13.4 mm) (normal bent) 85 m pd441000lgu-b10x-9jh 100 m pd441000lgu-c10x-9jh 100 2.2 to 3.6 c version m pd441000lgu-c12x-9jh 120 m pd441000lgu-d12x-9jh 120 1.8 to 3.6 d version m pd441000lgu-d15x-9jh 150 m pd441000lgu-b70x-9kh 32-pin plastic tsop (i) 70 2.7 to 3.6 b version m pd441000lgu-b85x-9kh (8 x 13.4 mm) (reverse bent) 85 m pd441000lgu-b10x-9kh 100 m pd441000lgu-c10x-9kh 100 2.2 to 3.6 c version m pd441000lgu-c12x-9kh 120 m pd441000lgu-d12x-9kh 120 1.8 to 3.6 d version m pd441000lgu-d15x-9kh 150 m pd441000lgz-b70x-kjh 32-pin plastic tsop (i) 70 2.7 to 3.6 b version m pd441000lgz-b85x-kjh (8 x 20 mm) (normal bent) 85 m pd441000lgz-b10x-kjh 100 m pd441000lgz-c10x-kjh 100 2.2 to 3.6 c version m pd441000lgz-c12x-kjh 120 m pd441000lgz-d12x-kjh 120 1.8 to 3.6 d version m pd441000lgz-d15x-kjh 150 m pd441000lgz-b70x-kkh 32-pin plastic tsop (i) 70 2.7 to 3.6 b version m pd441000lgz-b85x-kkh (8 x 20 mm) (reverse bent) 85 m pd441000lgz-b10x-kkh 100 m pd441000lgz-c10x-kkh 100 2.2 to 3.6 c version m pd441000lgz-c12x-kkh 120 m pd441000lgz-d12x-kkh 120 1.8 to 3.6 d version m pd441000lgz-d15x-kkh 150 m pd441000lf1-ba1-b70x note 36-pin plastic fpbga 70 2.7 to 3.6 b version m pd441000lf1-ba1-b85x note (6.0 x 6.0 mm) 85 m pd441000lf1-ba1-b10x note 100 m pd441000lf1-ba1-c10x note 100 2.2 to 3.6 c version m pd441000lf1-ba1-c12x note 120 m pd441000lf1-ba1-d12x note 120 1.8 to 3.6 d version m pd441000lf1-ba1-d15x note 150 note under development ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
data sheet m13714ej4v0ds00 3 m m m m pd441000l-x pin configuration (marking side) /xxx indicates active low si gnal. 32-pin plastic sop (525 mil) [ m m m m pd441000lgw-bxxx] [ m m m m pd441000lgw-cxxx] [ m m m m pd441000lgw-dxxx] nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc a15 ce2 /we a13 a8 a9 a11 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection ? ? ? ?
data sheet m13714ej4v0ds00 4 m m m m pd441000l-x 32-pin plastic tsop (i) (8 x 13.4 mm) (normal bent) [ m m m m pd441000lgu-bxxx-9jh] [ m m m m pd441000lgu-cxxx-9jh] [ m m m m pd441000lgu-dxxx-9jh] a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32-pin plastic tsop (i) (8 x 13.4 mm) (reverse bent) [ m m m m pd441000lgu-bxxx-9kh] [ m m m m pd441000lgu-cxxx-9kh] [ m m m m pd441000lgu-dxxx-9kh] /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection
data sheet m13714ej4v0ds00 5 m m m m pd441000l-x 32-pin plastic tsop (i) (8 x 20 mm) (normal bent) [ m m m m pd441000lgz-bxxx-kjh] [ m m m m pd441000lgz-cxxx-kjh] [ m m m m pd441000lgz-dxxx-kjh] a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32-pin plastic tsop (i) (8 x 20 mm) (reverse bent) [ m m m m pd441000lgz-bxxx-kkh] [ m m m m pd441000lgz-cxxx-kkh] [ m m m m pd441000lgz-dxxx-kkh] /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 /we ce2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection
data sheet m13714ej4v0ds00 6 m m m m pd441000l-x 36-pin plastic fpbga (6.0 x 6.0 mm) [ m m m m pd441000lf1-ba1-bxxx] [ m m m m pd441000lf1-ba1-cxxx] [ m m m m pd441000lf1-ba1-dxxx] 1 2 3 4 5 6 d f e b c a 6 5 4 3 2 1 bottom view top view top view bottom view 123456 654321 a a7 ce2 vcc a15 a13 a11 a a11 a13 a15 vcc ce2 a7 b a6 /we a16 ic a8 a9 b a9 a8 ic a16 /we a6 c a3 a5 ic ic a12 a14 c a14 a12 ic ic a5 a3 d /oe a0 ic ic a1 a4 d a4 a1 ic ic a0 /oe e /ce1 i/o3 i/o5 i/o6 i/o8 a2 e a2 i/o8 i/o6 i/o5 i/o3 /ce1 f i/o1 i/o2 i/o4 gnd i/o7 a10 f a10 i/o7 gnd i/o4 i/o2 i/o1 a0 - a16 : address inputs i/o1 - i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground ic note : internal connection note leave this pin unconnected or connect to gnd.
data sheet m13714ej4v0ds00 7 m m m m pd441000l-x block diagram address buffer row decoder memory cell array 1,048,576 bits input data controller a0 a16 i/o1 i/o8 sense/switch column decoder output data controller address buffer /ce1 ce2 /oe /we v cc gnd truth table /ce1 ce2 /oe /we mode i/o supply current h not selected high impedance i sb l l h h h output disable i cca lh l h read d out lh lwrite d in remark : dont care
data sheet m13714ej4v0ds00 8 m m m m pd441000l-x electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc C0.5 note to +4.6 v input / output voltage v t C0.5 note to v cc +0.5 v operating ambient temperature t a C25 to +85 c storage temperature t stg C55 to +125 c note C3.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition m pd441000l-bxxx m pd441000l-cxxx m pd441000l-dxxx unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 3.6 v high level input voltage v ih 2.7 v v cc 3.6 v2.4 v cc +0.5 2.4 v cc +0.5 2.4 v cc +0.5 v 2.2 v v cc < 2.7 vC C 2.0v cc +0.5 2.0 v cc +0.5 1.8 v v cc < 2.2 vCCCC1.6v cc +0.5 low level input voltage v il C0.3 note +0.5 C0.3 note +0.3 C0.3 note +0.2 v operating ambient temperature t a C25 +85 C25 +85 C25 +85 c note C3.0 v (min.) (pulse width: 30 ns)
data sheet m13714ej4v0ds00 9 m m m m pd441000l-x dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition m pd441000l-bxxx m pd441000l-cxxx m pd441000l-dxxx unit min. typ. max. min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a i/o leakage current i lo v io = 0 v to v cc , /ce1 = v ih or ce2 = v il or /we = v il or /oe = v ih C1.0 +1.0 C1.0 +1.0 C1.0 +1.0 m a operating supply i cca1 /ce1 = v il , ce2 = v ih , 232523252325ma current minimum cycle time, v cc 2.7 v 2023 2023 i i/o = 0ma v cc 2.2 v 1720 i cca2 /ce1 = v il , ce2 = v ih ,555 i i/o = 0ma v cc 2.7 v 4 4 v cc 2.2 v 3 i cca3 /ce1 0.2 v, ce2 3 v cc C 0.2 v, 444 cycle = 1mhz, i i/o = 0 ma, v cc 2.7 v 3 3 v il 0.2 v, v ih 3 v cc C 0.2 v v cc 2.2 v 3 standby supply i sb /ce1 = v ih or ce2 = v il 0.3 0.3 0.3 ma current i sb1 /ce1 3 v cc C 0.2 v, 0.05 2 0.05 2 0.05 2 m a ce2 3 v cc C 0.2 v v cc 2.7 v 0.04 2 0.04 2 v cc 2.2 v 0.03 1.5 i sb2 ce2 0.2 v 0.05 2 0.05 2 0.05 2 v cc 2.7 v 0.04 2 0.04 2 v cc 2.2 v 0.03 1.5 high level output v oh i oh = C0.5 ma 2.4 2.4 2.4 v voltage v cc 2.7 v 1.8 1.8 v cc 2.2 v 1.5 low level output v ol i ol = +1.0 ma 0.4 0.4 0.4 v voltage remarks 1. v in : input voltage 2. these dc characteristics are in common regardless of package types and access time. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage 2. these parameters are periodically sampled and not 100% tested.
data sheet m13714ej4v0ds00 10 m m m m pd441000l-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions m m m m pd441000l-b70x, m m m m pd441000l-b85x, m m m m pd441000l-b10x input waveform (rise and fall time 5 ns) test points 0.5 v 2.4 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load 1ttl + 50pf m m m m pd441000l-c10x, m m m m pd441000l-c12x input waveform (rise and fall time 5 ns) test points 0.3 v 2.0 v 1.1 v 1.1 v output waveform test points 1.1 v 1.1 v output load 1ttl + 30pf m m m m pd441000l-d12x, m m m m pd441000l-d15x input waveform (rise and fall time 5 ns) test points 0.2 v 1.6 v 0.9 v 0.9 v output waveform test points 0.9 v 0.9 v output load 1ttl + 30pf
data sheet m13714ej4v0ds00 11 m m m m pd441000l-x read cycle (1/3) (b version) parameter symbol m pd441000l-b70x m pd441000l-b85x m pd441000l-b10x unit notes min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns 1 /ce1 access time t co1 70 85 100 ns ce2 access time t co2 70 85 100 ns /oe to output valid t oe 35 45 50 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns 2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 555ns /ce1 to output in high impedance t hz1 25 30 35 ns ce2 to output in high impedance t hz2 25 30 35 ns /oe to output hold in high impedance t ohz 25 30 35 ns notes 1. see the output load. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle (2/3) (c version) parameter symbol m pd441000l-c10x m pd441000l-c12x unit notes min. max. min. max. read cycle time t rc 100 120 ns address access time t aa 100 120 ns 1 /ce1 access time t co1 100 120 ns ce2 access time t co2 100 120 ns /oe to output valid t oe 50 60 ns output hold from address change t oh 10 10 ns /ce1 to output in low impedance t lz1 10 10 ns 2 ce2 to output in low impedance t lz2 10 10 ns /oe to output in low impedance t olz 55ns /ce1 to output in high impedance t hz1 35 40 ns ce2 to output in high impedance t hz2 35 40 ns /oe to output hold in high impedance t ohz 35 40 ns notes 1. see the output load. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
data sheet m13714ej4v0ds00 12 m m m m pd441000l-x read cycle (3/3) (d version) parameter symbol m pd441000l-d12x m pd441000l-d15x unit notes min. max. min. max. read cycle time t rc 120 150 ns address access time t aa 120 150 ns 1 /ce1 access time t co1 120 150 ns ce2 access time t co2 120 150 ns /oe to output valid t oe 60 70 ns output hold from address change t oh 10 10 ns /ce1 to output in low impedance t lz1 10 10 ns 2 ce2 to output in low impedance t lz2 10 10 ns /oe to output in low impedance t olz 55ns /ce1 to output in high impedance t hz1 40 50 ns ce2 to output in high impedance t hz2 40 50 ns /oe to output hold in high impedance t ohz 40 50 ns notes 1. see the output load. 2. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. read cycle timing chart remark in read cycle, /we should be fixed to high level. high impedance data out /oe (input) ce2 (input) /ce1 (input) address (input) i/o (output) t hz2 t oh t hz1 t olz t oe t lz2 t co2 t lz1 t co1 t ohz t aa t rc
data sheet m13714ej4v0ds00 13 m m m m pd441000l-x write cycle (1/3) (b version) parameter symbol m pd441000l-b70x m pd441000l-b85x m pd441000l-b10x unit note min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /ce1 to end of write t cw1 55 70 80 ns ce2 to end of write t cw2 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 000ns write pulse width t wp 50 60 60 ns write recovery time t wr 000ns data valid to end of write t dw 35 35 40 ns data hold time t dh 000ns /we to output in high impedance t whz 25 30 35 ns 1 output active from end of write t ow 555ns note 1. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types. write cycle (2/3) (c version) parameter symbol m pd441000l-c10x m pd441000l-c12x unit note min. max. min. max. write cycle time t wc 100 120 ns /ce1 to end of write t cw1 80 100 ns ce2 to end of write t cw2 80 100 ns address valid to end of write t aw 80 100 ns address setup time t as 00ns write pulse width t wp 60 85 ns write recovery time t wr 00ns data valid to end of write t dw 45 60 ns data hold time t dh 00ns /we to output in high impedance t whz 35 40 ns 1 output active from end of write t ow 55ns note 1. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
data sheet m13714ej4v0ds00 14 m m m m pd441000l-x write cycle (3/3) (d version) parameter symbol m pd441000l-d12x m pd441000l-d15x unit note min. max. min. max. write cycle time t wc 120 150 ns /ce1 to end of write t cw1 100 120 ns ce2 to end of write t cw2 100 120 ns address valid to end of write t aw 100 120 ns address setup time t as 00ns write pulse width t wp 85 100 ns write recovery time t wr 00ns data valid to end of write t dw 60 80 ns data hold time t dh 00ns /we to output in high impedance t whz 40 50 ns 1 output active from end of write t ow 55ns note 1. the output load is 1ttl + 5 pf. remark these ac characteristics are in common regardless of package types.
data sheet m13714ej4v0ds00 15 m m m m pd441000l-x write cycle timing chart 1 (/we controlled) t wc t cw1 t aw t wp t as t wr t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address(input) /ce1 (input) /we (input) i/o (input/output) ce2 (input) t cw2 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remarks 1. write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
data sheet m13714ej4v0ds00 16 m m m m pd441000l-x write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t aw t wp t wr t dw t dh data in high impedance address (input) /ce1 (input) /we (input) i/o (input) high impedance ce2 (input) t cw2 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
data sheet m13714ej4v0ds00 17 m m m m pd441000l-x write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t aw t wp t wr t dw t dh data in high impedance address (input) ce2 (input) /we (input) i/o (input) high impedance /ce1 (input) t cw1 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. when i/o pins are in the output state, do not apply to the i/o pins signals that are opposite in phase with output signals. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
data sheet m13714ej4v0ds00 18 m m m m pd441000l-x low v cc data retention characteristics b version ( m m m m pd441000l-bxxx: t a = C25 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2v 2 3.6 v v ccdr2 ce2 0.2 v 2 3.6 data retention supply current i ccdr1 v cc = 3.0 v, /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v or ce2 0.2 v 0.05 2 note m a i ccdr2 v cc = 3.0 v, ce2 0.2 v 0.05 2 note chip deselection to data retention mode t cdr 0ns operation recovery time t r 5ms note 0.5 m a (t a 40 c) c, d version ( m m m m pd441000l-cxxx, m m m m pd441000l-dxxx: t a = C25 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v ccdr1 /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2v 1.5 3.6 v v ccdr2 ce2 0.2 v 1.5 3.6 data retention supply current i ccdr1 v cc = 3.0 v, /ce1 3 v cc - 0.2 v, ce2 3 v cc - 0.2 v or ce2 0.2 v 0.05 2 note m a i ccdr2 v cc = 3.0 v, ce2 0.2 v 0.05 2 note chip deselection to data retention mode t cdr 0ns operation recovery time t r 5ms note 0.5 m a (t a 40 c)
data sheet m13714ej4v0ds00 19 m m m m pd441000l-x data retention timing chart (1) /ce1 controlled t cdr data retention mode v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc /ce1 /ce1 3 v cc C 0.2 v gnd 3.0 v note v cc (min.) note b version: 2.7 v, c version: 2.2 v, d version: 1.8 v remark on the data retention mode by controlling /ce1, the input level of ce2 must be ce2 3 v cc - 0.2 v or ce2 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state. (2) ce2 controlled t cdr data retention mode 3.0 v v ih (min. ) v ccdr (min. ) v il (max. ) t r v cc ce2 ce2 0.2 v gnd note v cc (min.) note b version: 2.7 v, c version: 2.2 v, d version: 1.8 v remark the other pins (/ce1, address, i/o, /we, /oe) can be in high impedance state.
data sheet m13714ej4v0ds00 20 m m m m pd441000l-x package drawings 32 pin plastic sop (525 mil) a 32 17 detail of lead end 116 3 +7 ? p32gw-50-525a item millimeters inches a b c d e f g h i j k 20.61 max. 1.27 (t.p.) 2.95 max. 2.7 14.1 0.3 0.78 max. 0.812 max. 0.006 0.117 max. 0.555 0.012 0.445 0.031 max. note l m 0.12 0.8 0.2 1.4 0.2 11.3 0.005 0.031 +0.009 ?.008 each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.055 0.008 0.106 0.050 (t.p.) 0.20 0.008 n 0.10 0.004 0.016 0.40 0.15 0.05 +0.004 ?.002 +0.10 ?.05 +0.004 ?.003 +0.10 ?.05 f d m c m b n g e h k l j i ? ? ? ?
data sheet m13714ej4v0ds00 21 m m m m pd441000l-x 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9jh-1 b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.020 (t.p.) detail of lead end a 8.00.1 0.3150.004 h 12.40.2 0.4880.008 b t n d 0.220.05 0.009 +0.002 C0.003 g 1.00.05 0.039 +0.003 C0.009 i 11.80.1 0.465 +0.004 C0.005 j 0.80.2 0.031 +0.009 C0.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.10.05 0.0040.002 p 13.40.2 0.528 +0.008 C0.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.010 u 0.60.15 0.024 +0.006 C0.007 +5 C3 +5 C3 (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) m u l r q s d m c g k j 1 16 32 17 a 0.145 +0.025 C0.015 0.0060.001 h p i
data sheet m13714ej4v0ds00 22 m m m m pd441000l-x 32pin plastic tsop ( i ) (8x13.4) note (1) each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. item millimeters inches p32gu-50-9kh-1 b 0.45 max. 0.018 max. c 0.5 (t.p.) 0.020 (t.p.) detail of lead end a 8.00.1 0.3150.004 h 12.40.2 0.4880.008 b t n d 0.220.05 0.009 +0.002 C0.003 g 1.00.05 0.039 +0.003 C0.009 i 11.80.1 0.465 +0.004 C0.005 j 0.80.2 0.031 +0.009 C0.008 k l 0.5 0.020 m 0.08 0.003 n 0.08 0.003 q 0.10.05 0.0040.002 p 13.40.2 0.528 +0.008 C0.009 s 1.2 max. 0.048 max. r3 3 t 0.25 0.010 u 0.60.15 0.024 +0.006 C0.007 +5 C3 +5 C3 (2) "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.331 inch max.>) 1 16 32 17 m u l r q s d m c g a k j h p i 0.145 +0.025 C0.015 0.0060.001
data sheet m13714ej4v0ds00 23 m m m m pd441000l-x notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 18.40.1 0.1450.05 f 0.10 m 0.3150.004 0.018 max. 0.0040.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>) c r d m m l +0.002 C0.003 0.970.08 g 0.038 +0.004 C0.003 +0.005 C0.004 l 0.5 0.020 0.10 n 0.004 p 20.00.2 0.787 +0.009 C0.008 q3 3 +5 C3 +5 C3 0.25 r 0.010 s32gz-50-kjh1 s 0.600.15 0.024 +0.006 C0.007 +0.002 C0.003 j 0.80.2 0.031 +0.009 C0.008 1 16 32 17 s p g f e s q n k i b detail of lead end j a s 1. controlling dimension millimeter.
data sheet m13714ej4v0ds00 24 m m m m pd441000l-x notes 32 pin plastic tsop ( i ) (8 20) item millimeters inches a b c e i 8.00.1 0.5 (t.p.) 0.10.05 0.45 max. k 1.2 max. 18.40.1 0.1450.05 f 0.10 m 0.3150.004 0.018 max. 0.0040.002 0.724 0.006 0.048 max. 0.004 0.020 (t.p.) d 0.220.05 0.009 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 8.3 mm max. <0.327 inch max.>). c r d m m g +0.002 C0.003 0.970.08 g 0.038 +0.004 C0.003 +0.005 C0.004 l 0.5 0.020 0.10 n 0.004 p 20.00.2 0.787 +0.009 C0.008 q3 3 +5 C3 +5 C3 0.25 r 0.010 s32gz-50-kkh1 s 0.600.15 0.024 +0.006 C0.007 +0.002 C0.003 j 0.80.2 0.031 +0.009 C0.008 1 16 32 17 s n b a f e q s l k i p j detail of lead end s 1. controlling dimension millimeter.
data sheet m13714ej4v0ds00 25 m m m m pd441000l-x 36 pin plastic-fpbga (6.0 6.0) item millimeters b c 0.680.1 6.00.1 d 0.30.05 a 6.00.1 e f 0.1 1.1 max. h i 1.125 0.450.05 g 0.750.05 f b a g g h i f h e e d c c d
data sheet m13714ej4v0ds00 26 m m m m pd441000l-x recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd441000l-x. type of surface mount device m pd441000lgw-bx: 32-pin plastic sop (525 mil) m pd441000lgw-cx: 32-pin plastic sop (525 mil) m pd441000lgw-dx: 32-pin plastic sop (525 mil) m pd441000lgu-bx-9jh: 32-pin plastic tsop (i) (8 x 13.4 mm) (normal bent) m pd441000lgu-bx-9kh: 32-pin plastic tsop (i) (8 x 13.4 mm) (reverse bent) m pd441000lgu-cx-9jh: 32-pin plastic tsop (i) (8 x 13.4 mm) (normal bent) m pd441000lgu-cx-9kh: 32-pin plastic tsop (i) (8 x 13.4 mm) (reverse bent) m pd441000lgu-dx-9jh: 32-pin plastic tsop (i) (8 x 13.4 mm) (normal bent) m pd441000lgu-dx-9kh: 32-pin plastic tsop (i) (8 x 13.4 mm) (reverse bent) m pd441000lgz-bx-kjh: 32-pin plastic tsop (i) (8 x 20 mm) (normal bent) m pd441000lgz-bx-kkh: 32-pin plastic tsop (i) (8 x 20 mm) (reverse bent) m pd441000lgz-cx-kjh: 32-pin plastic tsop (i) (8 x 20 mm) (normal bent) m pd441000lgz-cx-kkh: 32-pin plastic tsop (i) (8 x 20 mm) (reverse bent) m pd441000lgz-dx-kjh: 32-pin plastic tsop (i) (8 x 20 mm) (normal bent) m pd441000lgz-dx-kkh: 32-pin plastic tsop (i) (8 x 20 mm) (reverse bent) m pd441000lf1-ba1-bx: 36-pin plastic fpbga (6.0 x 6.0 mm) m pd441000lf1-ba1-cx: 36-pin plastic fpbga (6.0 x 6.0 mm) m pd441000lf1-ba1-dx: 36-pin plastic fpbga (6.0 x 6.0 mm) ? ? ? ? ? ? ? ? ? ? ? ?
data sheet m13714ej4v0ds00 27 m m m m pd441000l-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd441000l-x [memo] the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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